In order to recover data from a received serial data stream, it is necessary for the receiving apparatus to include a sampling or retiming circuit which is "bit synchronised" with the received data stream. By the term bit synchronised, it is meant that the retiming circuit is clocked in such a way that it samples the data sufficiently near the middle of each received bit to be able to correctly identify whether the bit represents a zero or a one. In order to achieve bit synchronisation, it is therefore generally necessary for the retiming circuit to be clocked at substantially the same frequency as the incoming data stream and for the phase difference between the clocking signal and the data steam to be known.
Conventionally, this has been done using a Phase-Locked-Loop circuit (PLL) using the incoming data stream as a reference clock. Once the PLL is locked to the incoming data stream, its output will be the same frequency as the data stream and will have a fixed and known phase relationship to the data stream and can therefore be used to clock the retiming circuit. However, such an arrangement suffers from the significant drawback that a finite amount of time is required to lock the PLL to the incoming data stream which in turn gives rise to a finite delay (for example of the order of a few microseconds) before data from the data stream can be successfully recovered.
This delay in achieving bit synchronisation causes problems in itself where a large number of small data transfers are to take place (as opposed to only a small number of relatively large data sets to be transferred) as is common in many modern applications. Additionally, the delay in achieving bit synchronisation generally also leads to problems in obtaining frame synchronisation because it is not easily possible to establish exactly which bit in a frame is being detected when bit synchronisation is achieved. This not only generates further undesirable delays until frame synchronisation is achieved but also necessitates the provision of specialised circuitry and/or protocol systems which generally increase the cost and complexity of data communication systems.